FPGA Implementation of Low Power Recursive DFT for DTMF Application

The discrete Fourier transform(DFT) has been widely applied in the field of signal processing. There are lots of architectures available in literature which are of computing N point DFT type. Such algorithms are called as FFT computation algorithms. However in some applications we need to computer the DFT for some of selected output bin indices only. One of such example is signal monitoring and spectrum estimation technique in signal intelligence applications. The Dual-tone multi-frequency (DTMF) is also another example where we are specifically interested to see the energies at specific frequency values only. DTMF detection is used to detect DTMF signals in the presence of speech and dialing tone pulses. A low power recursive discrete Fourier transform(RDFT) design is proposed in this project. The proposed algorithm reduces the hardware complexity considerably . By this a considerable power saving is achieved. The recursive DFT is realized for DTMF detection applications . The architecture will be developed keeping DTMF requirements in consideration. The proposed algorithm will be implemented through VHDL. After verifying the simulation results the code will be synthesized on Xilinx FPGA. Modelsim Xilinx Edition (MXE) and Xilinx ISE will be used simulation and synthesis respectively. The Xilinx Chipscope tool will be used to test the FPGA inside results while the logic running on FPGA.